DRAM memory cell devices generally contain single transistor memory cells. A single transistor memory cell includes a selection transistor and a memory capacitor. Information is stored in the memory capacitor as electric charges and, under the control of a read transistor through a word line, the information can be read through a bit line.
In order to reliably hold the electric charges and enable information to be read and identified, the memory capacitor should have a high capacitance. However, as integration density increases and the area occupied by the single transistor memory cell is reduced, the area available for the memory capacitor decreases. Thus, it is desirable to have high capacitance in a small area.
One approach to fabricating memory capacitors is to form the memory capacitors within a trench in a substrate. Such trench capacitors can have a smoother surface topography, can be formed using fewer photolithography processes, and can have lower bit line capacitance compared to stack-type capacitors. Accordingly, trench type memory capacitors may be fabricated at a lower cost and may be driven with lower power than stack-type capacitors.
FIG. 1 is a cross-section of a DRAM that includes a conventional trench capacitor. Such a typical trench capacitor DRAM cell is disclosed in, for example, “Trench Capacitor DRAM Cell With Self-aligned Buried Strap”, published in IEDM 93-627. A substrate 100 is doped with P-type dopants. A trench capacitor 160 includes a trench etched deeply into the substrate 100, and N-type doped polysilicon 161 that fills the trench. The N-type doped polysilicon 161 serves as a top electrode (storage electrode). An N-type doped region 165 covers the bottom of the trench and serves as a bottom electrode. The N-type doped region 165 is also referred to as a buried plate. A dielectric layer 164 insulates the buried plate 165 and the N-type doped polysilicon 161. A buried N-type well 170 isolates a P-type well 151 from the substrate 100 and serves as a conduction bridge connecting the buried plates 165.
The DRAM cell also includes a transistor 110. The transistor 110 includes a gate 112 and diffusion regions 113 and 114. The diffusion regions 113 and 114 separated by a channel 117 are formed by implanting N-type dopants, such as phosphorous (P). A node diffusion region 125, also referred to as a node junction, couples the trench capacitor 160 to the transistor 110. The node diffusion region 125 is formed by out diffusion of dopants from the N-type doped polysilicon 161 that fills the trench via a buried strap 162.
By providing appropriate voltage to the gate 112 and a bit line 185 and activating the transistor 110, the trench capacitor 160 is accessed. Generally, the gate 112 forms a word line, and the diffusion region 113 is coupled to the bit line 185 in the DRAM cell array via a contact 183. The bit line 185 is insulated from the diffusion region 113 by an interlayer insulating layer 189.
Shallow trench isolation (STI) 180 is provided to insulate the DRAM from another cell or device. As illustrated in FIG. 1, a word line 120 is formed on a top portion of the trench and is insulated by the STI 180. The word line 120 is also known as a passing word line.
In addition, an insulating layer collar 168 is used to inhibit/prevent node junction leakage to the buried plate 165. Leakage decreases a time for sustaining cells and increases a refresh frequency, which lowers efficiency. A process of forming the insulating layer collar 168 includes deposition and local oxidation of silicon (LOCOS).
Common and well-known processes of forming the buried plate 165 include thermal diffusion, gas phase doping, and plasma immersion ion implantation, in which dopants are caused to diffuse out into the substrate 100 at the bottom of the trench.
A process for forming a buried plate of the trench capacitor using conventional thermal diffusion and a process of forming a collar using oxide layer deposition are illustrated in FIGS. 2A through 2D. First, as illustrated in FIG. 2A, a pad oxide layer 2 and a hard mask 4 are formed on a substrate 1. Then, a trench 6 is formed using the hard mask 4.
In FIG. 2B, a doped insulating layer 12, such as an arsenosilicate glass (ASG), is formed on the inner wall and bottom of the trench 6. Then, the bottom of the trench 6 is filled with photoresist 14. As a result, the doped insulating layer 12 on the top inner wall of the trench 6 remains exposed.
The doped insulating layer 12 on the top of the trench 6 is removed by etching. Thus, a doped insulation layer 12a remains only at the bottom portion of the trench 6. Then, a cap oxide layer, such as teraethylorthosilicate (TEOS) layer, is deposited on the trench 6. The cap oxide layer is recessed to expose the photoresist 14, thereby forming a collar 16. This process is illustrated in FIG. 2C.
Referring to FIG. 2D, after removing the photoresist 14 of FIG. 2C, a diffusion region 18 is formed by impurities inside the doped insulating layer 12 diffusing into the substrate 1 through a thermal process on the doped insulting layer 12 and other layers. This diffusion region 18 is a buried plate.
Afterwards, the rest of the process is performed to form the structure illustrated in FIG. 1. A trench capacitor that is fabricated according to the processes described above may use more than seven process operations to form the collar 16 and the buried plate 18. Also, the ASG can include an organic precursor such as TEOS and triethylarsenate (TEAS) or triethylorthoacetate (TEOA). It may be difficult to use ASG in a low-pressure chemical vapor deposition (LPCVD) process because these precursors can cause defects and non-uniformity in the substrate. Moreover, ASG can be relatively expensive.
A process for forming a buried plate of a trench capacitor using conventional gas phase doping or plasma immersion ion implantation, and forming a collar using a LOCOS process, are illustrated in FIGS. 3A through 3C. A process for forming a buried strap is illustrated in FIGS. 3D through 3F.
First, as illustrated in FIG. 3A, a pad oxide layer 22 and a hard mask 24 are formed on a substrate 21. Then, a trench 26 is formed using the hard mask 24. After forming an insulating layer, such as a silicon nitride layer, on the inner wall and bottom of the trench 26, the bottom of the trench 26 is filled with photoresist 34. Then, the insulating layer is removed from the top inner wall of the trench 26 by etching. As a result, an oxidation prevention layer 32 remains only at the bottom portion of the trench 26, and the top inner wall of the trench 26 is exposed.
Next, as illustrated in FIG. 3B, after removing the photoresist 34 of FIG. 3A, a LOCOS-type collar 36 is formed by oxidizing the exposed inner wall of the trench 26.
The oxidation prevention layer 32 is removed as shown in FIG. 3C. Here, the trench 26 of FIG. 3B may be expanded to form a trench 26a with a larger bottom width. Then, a buried plate 38 is formed on the inner walls and at the bottom of the trench 26a by gas phase doping or a plasma immersion ion implantation process.
Afterwards, the rest of the process is performed to form the structure illustrated in FIG. 1. The gas phase doping and the plasma immersion ion implantation processes may each be simpler than the thermal diffusion process. However, it may be difficult with the gas phase doping and/or the plasma immersion ion implantation processes to maintain a uniform doping profile and at least a predetermined doping density in a trench with a high aspect ratio. Even if the LOCOS process, which is simpler than the deposition and etching to form the collar 36 as shown in FIG. 2C, is used, more than six processes may be needed.
In addition, after forming a dielectric layer (not shown) and doped polysilicon 40 as in FIG. 3D, a buried strap (162 of FIG. 1) that connects a transistor and a capacitor needs to be formed. As illustrated in FIG. 3E, a process is needed to remove a portion of the collar 36 to form collar patterns 36a and then expose regions 42 on which the buried strap is to be formed. Then, a buried strap 44 is formed as illustrated in FIG. 3F.
However, according to the above-mentioned processes, the thickness of the collar 36 may be limited because the oxidation process can only be performed as much as the oxidation prevention layer 32 can endure. Accordingly, current leakage of the buried plate 38 and the buried strap 44 may not be adequately controlled. Furthermore, a separate process is required to form a buried N-type well (170 of FIG. 1) for electrical connection.